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New Industry Features
- - - - - - - Programmable time sequencing Integrated oscillator and dividers No crystal required Quad voltage monitors Remote delay selection Remote monitor/switch diagnostics Cascade delays of multiple devices
X80140/41/42/43/44
Voltage Supervisor/Sequencer
Quad Programmable Time Delay with Local/ Remote Voltage Monitors
* * * * * * 100 ms to 5 secs Selectable Delay Switches ATE or Data Acquisition Timing Applications Datapath/Memory Timing Applications Data Pipeline Timing Applications Batch Timer/Sequencers Adjustable Duty Cycle Applications
FEATURES * Quad voltage Monitor and Sequencing -- Four independent voltage monitors -- Four time delay circuits (in circuit programmable) -- Remote delay via SMBus -- Factory Programmable voltage thresholds -- Sequence up to 5 power supplies. * Fault detection register -- Remote diagnostics of voltage fail event. * Debounced manual reset input * Manufacturing/Configuration Memory -- 2Kbits of EEPROM -- 400kHz SMBus interface * Available packages -- 20-lead Quad No-Lead Frame (QFN -- 5 x 5 mm) APPLICATIONS * * * * * * * * * * * General Purpose Timers Long Time Delay Generation Cycle Timers / Waveform Generation ON/OFF Delay Timers Supply Sequencing for Distributed Power Programmable Delay Event Sequencing Multiple DC-DC ON/OFF Sequencing Voltage Window Monitoring with Reset ON/OFF switches with Programmable Delay Voltage Supervisor with Programmable Output Delays Databus Power Sequencing
DESCRIPTION The X80140 is a voltage supervisor/sequencer with four built in voltage monitors. This allows the designer to monitor up to four voltages and sequence up to five events. Low voltage detection circuitry protects the system from power supply failure or "brown out" conditions, resetting the system and resequencing the voltages when any of the monitored inputs fall below the minimum threshold level. The RESET pin is active until all monitored voltages reach proper operating levels and stabilize for a selectable period of time. Five common low voltage combinations are available, however, Xicor's unique circuits allow the any voltage monitor threshold to be reprogrammed for special needs or for applications requiring higher precision. A manual reset input provides debounce circuitry for minimum reset component count. Activating the manual reset both controls the RESET output and resequences the supplies through control of the ViGDO pins. The X80140 has 2kb of EEPROM for system configuration, manufacturing or maintenance information. This memory is protected to prevent inadvertent changes to the contents.
BLOCK DIAGRAM RESET SDA
Bus Interface
VSS
VCC MR
POR
Reset Logic and Delay
Control and Fault Registers
SCL WP A0 A1
VP
VMON Logic OSC Divider
Reset
EEPROM 2kbits 4
VSS
V1MON
VREF1
V1GDO
4
Select 0.1s 0.5s 1s 5s
V2GDO V3GDO V4GDO
V2MON
VREF2
delay1 delay2
V3MON
VREF3
delay3 delay4
Delay circuit repeated 4 times
V4MON
VREF4
VSS
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VSS
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X80140/41/42/43/44 - Preliminary Information
PIN OUTS QFN package (Top view) ORDERING INFORMATION ORDER NUMBER VREF1 X80140Q20I 4.5 X80141Q20I 4.5 X80142Q20I 3.0 X80143Q20I 3.0 X80144Q20I 2.25 VREF2 3.0 2.25 2.25 2.25 2.25 VREF3 2.25 0.9 1.7 0.9 0.9 VREF4 0.9 0.9 0.9 0.9 0.9 Package QFN QFN QFN QFN QFN
VCC
VSS
20 19 18 17 16 V4GDO V4MON V3GDO V3MON V2GDO 1 2 3 4 5 6 7 8 9 10 15 14 WP RESET V1GDO V1MON SCL
(5mm x 5mm)
NC
MR 13 12 11 SDA
A0 V2MON
ABSOLUTE MAXIMUM RATINGS
DNC
VP
A1
COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Industrial (I) Min. -40C Supply Voltage VCC = 4.5 to 5.5V Max. +85C
Temperature under bias ................... -65C to +135C Storage temperature ........................ -65C to +150C ViMON pins (i = 1 to 4) ......................................... 5.5V ViGDO pins (i = 1 to 4) ........................................ 5.5V RESET pin ........................................................... 5.5V SDA, SCL, WP, A0, A1 pins .................................. 5.5V MR pin.................................................................. 5.5V VP pin .................................................................... 14V D.C. output current ............................................... 5mA Lead temperature (soldering, 10 seconds)........ 300C
ELECTRICAL CHARACTERISTICS (Standard Settings) (Over the recommended operating conditions unless otherwise specified). Symbol Parameter Min. 4.5 1.0 9 Typ. Max. 5.5 2.5 12 10 10 15 Unit Test Conditions
DC Characteristics Supply Operating Range VCC ICC Supply Current VP(3) EEPROM programming voltage IP Programming Current ILI Input Leakage Current (MR) ILO Output Leakage Current (V1GDO, V2GDO, V3GDO, V4GDO, RESET) Input LOW Voltage (MR) VIL VIH Input HIGH Voltage (MR) VOL Output LOW Voltage (RESET, V1GDO, V2GDO, V3GDO, V4GDO)
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V mA fSCL = 0 kHz V mA A VIL = GND to VCC A
-0.5 5 x 0.7
5 x 0.3 5.5 0.4
V V V
IOL = 4.0 mA
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X80140/41/42/43/44 - Preliminary Information
ELECTRICAL CHARACTERISTICS (Continued)(Standard Settings) (Over the recommended operating conditions unless otherwise specified). Symbol COUT(1) Parameter Output Capacitance (RESET, V1GDO, V2GDO, V3GDO, V4GDO) V1MON Trip Point Voltage (Range) Min. Typ. Max. 8 Unit Test Conditions pF VOUT = 0V
VREF1
X80140 X80141 X80142 X80143 X80144
VREF2 V2MON Trip Point Voltage
X80140 X80141 X80142 X80143 X80144
VREF3 V3MON Trip Point Voltage
X80140 X80141 X80142 X80143 X80144
VREF4 VREF V4MON Trip Point Voltage
All Devices
Voltage Reference Long Term Drift AC Characteristics tMR(3) Minimum time high for reset valid on the MR pin Delay from MR enable to tMRE(3) V1GDO HIGH tRESET_E(3) Delay from ViGDO to RESET valid LOW tDPOR(3) Internal Device Delay on power up tTO(3) ViGDO turn off time
2.20 4.45 4.45 2.95 2.95 2.20 2.20 2.95 2.20 2.20 2.20 2.20 0.85 2.20 0.85 1.65 0.85 0.85 0.85 0.85 0 5
4.50 4.50 3.00 3.00 2.25 3.00 2.25 2.25 2.25 2.25 2.25 0.90 1.70 0.90 0.90 0.90
4.70 4.55 4.55 3.05 3.05 2.30 4.70 3.05 2.30 2.30 2.30 2.30 3.5 2.30 0.95 1.75 0.95 0.95 3.5 0.95 -100
V
V
V
V mV 10 years s
1.6 1 45 50 50 55
s s ms ns
ELECTRICAL CHARACTERISTICS (Programmable Parameters) (Over the recommended operating conditions unless otherwise specified). Symbol tSPOR Parameter Delay before RESET assertion TPOR1 = 0 TPOR0 = 0 TPOR1 = 0 TPOR0 = 1 TPOR1 = 1 TPOR0 = 0 TPOR1 = 1 TPOR0 = 1 Time Delay used in Power Sequencing (i = 1 to 4) TiD1 = 0 TiD0 = 0 TiD1 = 0 TiD0 = 1 TiD1 = 1 TiD0 = 0 TiD1 = 1 TiD0 = 1 Min. 90 450 0.9 4.5 Typ. 100 500 1 5 Max. 110 550 1.1 5.5 Unit ms ms s s Test Conditions Factory Default (3) (3) (3)
tDELAYi
90 450 0.9 4.5
100 500 1 5
110 550 1.1 5.5
ms ms s s
Factory Default (3) (3) (3)
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X80140/41/42/43/44 - Preliminary Information
EQUIVALENT A.C. OUTPUT LOAD CIRCUIT
5V 5V 4.6K RESET SDA 30pF 30pF V1GDO, V2GDO, V3GDO, V4GDO 5V 4.6K
A.C. TEST CONDITIONS Input pulse levels Input rise and fall times Input and output timing levels Output load
VCC x 0.1 to VCC x 0.9
10ns
4.6K
VCC x 0.5
Standard output load
30pF
Figure 1. Initial Power up and delay timing Initial Power-up VCC
VREFi ViMON
tDPOR
tDELAYi
tTO
tDELAYi i = 1, 2, 3, 4
ViGDO
Figure 2. Manual Reset (MR) MR tMR
SYMBOL TABLE
WAVEFORM INPUTS
Must be steady May change from LOW to HIGH
OUTPUTS
Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known
ViGDO tMRE RESET tMRE tDELAYi + tSPOR tDELAYi
May change from HIGH to LOW Don't Care: Changes Allowed
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Figure 3. ViGDO, RESET Timings
MR ViMON (i= 1 to 4) V1GDO
tDELAY1 tDELAY2
tDELAY1 tDELAY2 tDELAY3
V2GDO tDELAY3 V3GDO tDELAY4 V4GDO tSPOR RESET tRESET_E
Any ViGDO (1st occurance)
tDELAY4 tSPOR
SERIAL INTERFACE
(Over the recommended operating conditions unless otherwise specified).
Symbol Parameter Min. Typ. Max. 2.5 Unit mA Test Conditions VIL = VCC x 0.1 VIH = VCC x 0.9, fSCL = 400kHz VIL = GND to VCC VSDA = GND to VCC Device is in Standby DC Characteristics ICC1 Active Supply Current (VCC) Read or Write to Memory or registers ILI ILO VIL VIH VHYS Input Leakage Current (SCL, WP, A0, A1) Output Leakage Current (SDA) Input LOW Voltage (SDA, SCL, WP, A0, A1) Input HIGH Voltage (SDA, SCL, WP, A0, A1) Schmidt Trigger Input Hysteresis * Fixed input level * VCC related level Output LOW Voltage (SDA)
10 10 -0.5 5 x 0.7 5 x 0.3 5.5
A A V V
0.2 .05 x 5 0.4
VOL
V V V
IOL = 4.0 mA
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X80140/41/42/43/44 - Preliminary Information
SERIAL INTERFACE (Continued)
(Over the recommended operating conditions unless otherwise specified).
Symbol Parameter Min. Typ. Max. 400 50 0.1 1.3 1.3 0.6 0.6 0.6 100 0 0.6 50 20 +.1Cb 20 +.1Cb 0.6 0 0.6 0 0.6 5 1.5 Unit kHz ns s s s s s s ns s s ns ns ns s s s s s pF ms Test Conditions AC Characteristics fSCL SCL Clock Frequency tIN Pulse width Suppression Time at inputs SCL LOW to SDA Data Out Valid tAA(1) tBUF(1) Time the bus is free before start of new transmission Clock LOW Time tLOW tHIGH Clock HIGH Time tSU:STA Start Condition Setup Time tHD:STA Start Condition Hold Time tSU:DAT Data In Setup Time tHD:DAT Data In Hold Time tSU:STO Stop Condition Setup Time Data Output Hold Time tDH(1) tR(1) SDA and SCL Rise Time tF(1) SDA and SCL Fall Time tSU:WP WP Setup Time tHD:WP WP Hold Time tSU:ADR A0, A1 Setup Time tHD:ADR A0, A1 Hold Time tSU:VP VP Setup Time Cb(3) Capacitive load for each bus line tWC(2) EEPROM Write Cycle Time
300 300
400 10
Note: (1) This parameter is based on characterization data.
(2) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. (3) This parameter is not 100% tested.
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X80140/41/42/43/44 - Preliminary Information
TIMING DIAGRAMS Figure 4. Bus Timing
tF SCL tSU:STA SDA IN tHD:STA tSU:DAT tHD:DAT tSU:STO tHIGH tLOW tR
tAA SDA OUT
tDH
tBUF
Figure 5. WP, A0, A1, VP Pin Timing
START SCL Clk 1 Slave Address Byte SDA IN tSU:WP WP tSU:ADR A1, A0 VP tSU:VP tWC tHD:ADR tHD:WP Clk 9
Figure 6. Write Cycle Timing
SCL
SDA
8th Bit of Last Byte
ACK tWC Stop Condition Start Condition
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X80140/41/42/43/44 - Preliminary Information
PIN CONFIGURATION Pin 10 Description Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a pull up resistor and the input buffer is always active (not gated). SCL Serial Clock. The Serial Clock controls the serial bus timing for data input and output. V1MON V1 Voltage Monitor Input. First voltage monitor pin. If unused connect to VCC. V1GDO V1 Voltage Good Delay Output (Active LOW). This open drain output goes HIGH when V1MON is less than VREF1 and goes LOW when V1MON is greater than VREF1. There is user selectable delay circuitry on this pin. RESET RESET Output. This open drain pin is an active LOW output. This pin will be active until all ViGDO pins go inactive and the power sequencing is complete. This pin will be released after a programmable delay. WP Write Protect. Input Pin. WP HIGH (in conjunction with WPEN bit=1) prevents writes to any memory location in the device. It has an internal pull-down resistor. (>10M typical) MR Manual Reset. Pulling the MR pin HIGH initiates a RESET. The MR signal must be held HIGH for 5secs. It has an internal pull-down resistor. (>10M typical) VSS Ground Input. NC No Connect. No internal connections. A0 Address Select Input. It has an internal pull-down resistor. (>10M typical) The A0 and A1 bits allow for up to 4 X80140 devices to be used on the same SMBus serial interface. VCC Supply Voltage. Name SDA
X80140/1/2/3/4
VCC VSS NC MR 15 14 A0
20 19 18 17 16 V4GDO V4MON V3GDO V3MON V2GDO 1 2 3 4 5 6 7 8 9 10 WP RESET V1GDO V1MON SCL
11 12 13
(5mm x 5mm)
13 12 11
V2MON
DNC
A1
SDA
VP
PIN DESCRIPTIONS Pin 1 Name Description V4GDO V4 Voltage Good Delay Output (Active LOW). This open drain output goes HIGH when V4MON is less than VREF4 and goes LOW when V4MON is greater than VREF4. There is user selectable delay circuitry on this pin. V4MON V4 Voltage Monitor Input. Fourth voltage monitor pin. If unused connect to VCC. V3GDO V3 Voltage Good Delay Output (Active LOW). This open drain output goes HIGH when V3MON is less than VREF3 and goes LOW when V3MON is greater than VREF3. There is user selectable delay circuitry on this pin. V3MON V3 Voltage Monitor Input. Third voltage monitor pin. If unused connect to VCC. V2GDO V2 Voltage Good Delay Output (Active LOW). This open drain output goes HIGH when V2MON is less than VREF2 and goes LOW when V2MON is greater than VREF2. There is user selectable delay circuitry on this pin. VP EEPROM programming Voltage. V2MON V2 Voltage Monitor Input. Second voltage monitor pin. If unused connect to VCC. DNC Do Not Connect. A1 Address Select Input. It has an internal pulldown resistor. (>10M typical) The A0 and A1 bits allow for up to 4 X80140 devices to be used on the same SMBus serial interface.
14
15
2 3
16
4 5
17 18 19
20
6 7 8 9
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X80140/41/42/43/44 - Preliminary Information
FUNCTIONAL DESCRIPTION Power On Reset and System Reset With Delay Application of power to the X80140 activates a Power On Reset circuit that pulls the RESET pin active. This signal, if used, prevents the system microprocessor from starting to operate while there is insufficient voltage on any of the supplies. This circuit also does the following: - It prevents the processor from operating prior to stabilization of the oscillator. - It allows time for an FPGA to download its configuration prior to initialization of the circuit. - It prevents communication to the EEPROM during unstable power conditions, greatly reducing the likelihood of data corruption on power up. - It allows time for all supplies to turn on and stabilize prior to system initialization. The POR/RESET circuit is activated when all voltages are within specified ranges and the V1GDO, V2GDO, V3GDO, and V4GDO time-out conditions are met. The POR/RESET circuit will then wait tSPOR and de-assert the RESET pin. The POR delay may be changed by setting the TPOR bits in register CR2. The delay can be set to 100 ms, 500 ms, 1 second, or 5 seconds. Table 1. POR RESET Delay Options tSPOR delay before RESET assertion 100 milliseconds (default) 500 milliseconds 1 second 5 seconds Table 2. ViGDO output Time Delay Options
TiD1 TiD0 tDELAYi 0 0 100ms (default) 0 1 500ms 1 0 1 secs 1 1 5 secs where i is the specific voltage monitor (i = 1 to 4). Fault Detection The X80140 contains a Fault Detection Register (FDR) that provides the user the status of the causes for a RESET pin active (See Table 20). At power-up, the FDR is defaulted to all "0". The system needs to initialize the register to all "1" before the actual monitoring can take place. In the event that any one of the monitored sources fail, the corresponding bit in the register changes from a "1" to a "0" to indicate the failure. When a RESET is detected by the main controller, the controller should read the FDR and note the cause of the fault. After reading the register, the controller can reset the register bit back to all "1" in preparation for future failure conditions. Flexible Power Sequencing of Multiple Power Supplies The X80140 provides several circuits such as multiple voltage monitors, programmable delays, and output drive signals that can be used to set up flexible power monitoring or sequencing schemes system power supplies. Below are two examples: 1) Power Up of Supplies In Parallel Using Programmable Delays. (See Figure 7 and Figure 8). The X80140 monitors several power supplies, powered by the same source voltage, that all begin power up at the same time. Each voltage source is fed into the ViMON inputs to the X80140. The ViMON inputs monitor the voltage to make sure it has reached the minimum desired level. When each voltage monitor determines that its input is good, a counter starts. After the programmed delay time, the X80140 sets the ViGDO signals LOW. Any individual voltage failure can be viewed in the Fault Detection Register. In the factory default condition, each ViGDO output is instructed to go LOW 100ms after the input voltage reaches its threshold. However, each ViGDO delay is individually selectable as 100ms, 500ms, 1s and 5s. The delay times are changed via the SMBus during calibration of the system.
TPOR1 TPOR0 0 0 0 1 1 0 1 1 Manual Reset
The manual reset option allows a hardware reset of the power sequencing pins. These can be used to recover the system in the event of an abnormal operating condition. Activating the MR pin for more than 5us sets all of the ViGDO outputs and the RESET output active (LOW). When MR is released (and if all supplies are still at their proper operating voltage) then the ViGDO and RESET pins will be released after their programmed delay periods. (See Figure 3.) Quad Voltage Monitoring X80140 monitors 4 voltage inputs. When the ViMON (i=1-4) input is detected to be above the input threshold, the output ViGDO (i = 1 to 4) goes inactive (LOW). The ViGDO signal is deasserted after a delay of 100ms. This delay can be changed on each ViGDO output individually with bits in register CR3. The delay can be 100ms, 500ms, 1s and 5s. Each ViGDO signal remains active until its associated ViMON input rises above the threshold.
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Figure 7. Example Application of Parallel Power Control.
Power Supplies 5V 3.3V 2.5V 1.2V
Figure 8. Parallel Power Control - Timing
Can Choose Different Delays for each Voltage Monitor Programmable Delay
V1MON
On/Off On/Off On/Off
tDELAY1 V1GDO
100ms 500ms 1 sec 5 secs
V4MON
X80140/41/42/43/44
V4GDO V4MON V3GDO V3MON V2GDO V2MON V1GDO V1MON RESET MR
C VCC1 IRQ RESET VCC2 FPGA VCC1 VCC2 ASIC VCC1
VCC2
tDELAY4 V4GDO tSPOR RESET
Programmable Delay
Programmable Delay
Timing not to scale
2)
Power Up of Supplies Via Relay Sequencing Using Voltage Monitors (see Figure 10 and Figure 9). Several power supplies and their respective power up start times can be controlled using the X80140 such that each of the power supplies will start in a relay sequencing fashion. In the following example, the 1st supply is allowed to power up when the input regulated supply reaches an acceptable threshold. Subsequent supplies power up after the prior supply has reached its operating voltage. This configuration ensures that each subsequent power supply turns on after the preceding supplies voltage output is valid. Again, the X80140 offers programmable delays for each voltage monitor and this delay is selectable via the SMBus during calibration of the system.
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X80140/41/42/43/44 - Preliminary Information
Figure 9. Example of Relay Power Supply Sequencing
12V
Power 5V Supply On/Off 1.2V Power Supply On/Off Power 3.3V Supply On/Off Power 2.5V Supply On/Off
C RESET
VCC1 VCC2
VCC1 VCC2
FPGA
X80140/41/42/43
V4GDO V4MON VCC V3GDO V3MON V2GDO V2MON V1MON V1GDO 5V RESET MR
VCC1
VCC2
ASIC
Figure 10.Relay Sequencing of DC-DC Supplies. (Timing)
V1MON (12V) tDELAY1 V1GDO Power Supply #2 OUTPUT (5V) tDELAY2 V2GDO Power Supply #3 OUTPUT (1.2V) tDELAY3 V1MON threshold Programmable Delay 100ms 500ms 1sec 5sec Power Supply #2 ON 100ms 500ms 1sec Programmable 5sec Delay Power Supply #3 ON V3MON threshold Programmable Delay 100ms 500ms 1sec 5sec Power Supply #4 ON V4MON threshold tDELAY4 V4GDO Power Supply #5 OUTPUT (2.5V) RESET Programmable Delay 100ms 500ms 1sec 5sec V2MON threshold Timing Not To Scale Example: Five Independent Power Supplies in relay timing
V3GDO Power Supply #4 OUTPUT (3.3V)
tSPOR
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CONTROL REGISTERS AND MEMORY The user addressable internal control, status and memory components of the X80140 can be split up into three parts: - Control Register (CR) - Fault Detection Register (FDR) - EEPROM array Registers The Control Registers and Fault Detection Register are summarized in Table 4. Changing bits in these registers change the operation of the device or clear fault conditions. Reading bits from these registers provides information about device configuration or fault conditions. Reads and writes are done through the SMBus serial port. All of the Control Register bits are nonvolatile (except for the WEL bit), so they do not change when power is removed. The values of the Register Block can be read at any time by performing a random read (see Serial Interface) at the specific byte address location. Only one byte is read by each register read operation. Bits in the registers can be modified by performing a single byte write operation directly to the address of the register and only one data byte can change for each register write operation. EEPROM Array The X80140 contains a 2kbit EEPROM memory array. This array can contain information about manufacturing location and dates, board configuration, fault conditions, service history, etc. Access to this memory is through the SMBus serial port. Read and write operations are similar to those of the control registers, but a single command can write up to 16 bytes at one time. A single read command can return the entire contents of the EEPROM memory. Register and memory protection In order to reduce the possibility of inadvertent changes to either a control register of the contents of memory, several protection mechanisms are built into the X80140. These are a Write Enable Latch, Block Protect bits, a Write Protect Enable bit and a Write Protect pin. Table 3. WEL LOW HIGH HIGH HIGH Write Protect Conditions WP X LOW X HIGH WPEN X X LOW HIGH Memory Array NOT Block Protected Writes Blocked Writes Enabled Writes Enabled Writes Enabled Memory Array Block Protected Writes Blocked Writes Blocked Writes Blocked Writes Blocked Writes to CR1, CR2, CR3, CR4 Writes Blocked Writes Enabled Writes Enabled Writes Blocked Protection Hardware Software Software Hardware WEL: Write Enable Latch A write enable latch (WEL) bit controls write accesses to the nonvolatile registers and the EEPROM memory array in the X80140. This bit is a volatile latch that powers up in the LOW (disabled) state. While the WEL bit is LOW, writes to any address (registers or memory) will be ignored. The WEL bit is set by writing a "1" to the WEL bit and zeroes to the other bits of the control register 0 (CR0). It is important to write only 00h or 80h to the CR0 register. Once set, WEL remains set until either it is reset to 0 (by writing a "0" to the WEL bit and zeroes to the other bits of the control register) or until the part powers up again. Note, a write to FDR or RSR does not require that WEL=1. BP1 and BP0: Block Protect Bits The Block Protect Bits, BP1 and BP0, determines which blocks of the memory array are write protected. A write to a protected block of memory is ignored. The block protect bits will prevent write operations to one of four segments of the array. BP1 BP0 Protected Addresses (Size) None (Default) C0h - FFh (64 bytes) 80h - FFh (128 bytes) 00h - FFh (256 bytes) Array Lock None (Default) Upper 1/4 Upper 1/2 All
0 0 1 1
0 1 0 1
WPEN: Write Protect Enable The Write Protect pin and Write Protect Enable bit in the CR1 register control the Programmable Hardware Write Protect feature. Hardware Protection is enabled when the WP pin is HIGH and WPEN bit is HIGH and disabled when WP pin is LOW or the WPEN bit is LOW. When the chip is Hardware Write Protected, non-volatile writes to all control registers (CR1, CR2, CR3, and CR4) are disabled including BP bits, the WPEN bit itself, and the blocked sections in the memory Array. Only the section of the memory array that are not block protected can be written. Non volatile Programming Voltage (VP) Nonvolatile writes require that a programming voltage be applied to the VP for the duration of a nonvolatile write operation.
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Table 4. Byte Addr. 00H 01H 02H 03H FF Table 5. Register Address Map Bit Name CR0 CR1 CR2 CR3 FDR Control/Status Write Enable EEPROM Block Control POR Timing ViGDO Time Delay Fault Detection Register 7 WEL WPEN 0 T4D1 0 6 0 0 0 T4D0 0 5 0 0 0 T3D1 0 4 0 BP1 0 T3D0 0 3 0 BP0 2 0 0 1 0 0 0 T1D1 V20S 0 0 0 0 T1D0 V10S Memory Type Volatile EEPROM EEPROM EEPROM Volatile
TPOR1 TPOR0 T2D1 V40S T2D0 V30S
Hardware/Software Control and Fault Detection Bits Summary Control/ Location(s) Status Register Bits Description (See Functional for Details) Bits Software Control Bits WEL CR0 7 WEL = 1 enables write operations to the control registers and EEPROM. WEL = 0 prevents write operations. WPEN = 1 (and WP pin HIGH) prevents writes to the control registers and the EEPROM. BP1=0, BP0=0 : No EEPROM memory protected. BP1=0, BP0=1 : Upper 1/4 of EEPROM memory protected BP1=1, BP0=0 : Upper 1/2 of EEPROM memory protected. BP1=1, BP0=1 : All of EEPROM memory protected. TPOR1=0, TPOR0=0 : RESET delay = 100ms TPOR1=0, TPOR0=1 : RESET delay = 500ms TPOR1=1, TPOR0=0 : RESET delay = 1s TPOR1=1, TPOR0=1 : RESET delay = 5s TiD1=0, TiD0=0 : ViGDO delay = 100ms TiD1=0, TiD0=1 : ViGDO delay = 500ms TiD1=1, TiD0=0 : ViGDO delay = 1s TiD1=1, TiD0=1 : ViGDO delay = 5s
Operation EEPROM Write Enable
EEPROM Write Protect EEPROM Block Protect
WPEN BP1 BP0
CR1 CR1
7 4:3
RESET Time Delay
TPOR1 TPOR0
CR2
3:2
V1GDO Time Delay V2GDO Time Delay V3GDO Time Delay V4GDO Time Delay
T1D1 T1D0 T2D1 T2D0 T3D1 T3D0 T4D1 T4D0 V1OS V2OS V3OS V4OS
CR3 CR3 CR3 CR3
1:0 3:2 5:4 7:6
Status Bits 1st Voltage Monitor 2nd Voltage Monitor 3rd Voltage Monitor 4th Voltage Monitor FDR FDR FDR FDR 0 1 2 3 V1OS = 0 : V1GDO pin has been asserted (must be preset to 1). V2OS = 0 : V2GDO pin has been asserted (must be preset to 1). V3OS = 0 : V3GDO pin has been asserted (must be preset to 1). V4OS = 0 : V4GDO pin has been asserted (must be preset to 1).
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X80140/41/42/43/44 - Preliminary Information
BUS INTERFACE INFORMATION In the read mode, the device will transmit eight bits of data, release the SDA line, then monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the device will continue to transmit data. The device will terminate further data transmissions if an acknowledge is not detected. The master must then issue a stop condition to return the device to Standby mode and place the device into a known state. Figure 11.Valid Start and Stop Conditions
Interface Conventions
The device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is called the master and the device being controlled is called the slave. The master always initiates data transfers, and provides the clock for both transmit and receive operations. Therefore, the devices in this family operate as slaves in all applications. It should be noted that the ninth clock cycle of the read operation is not a "don't care." To terminate a read operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during the ninth clock cycle and then issue a stop condition. Serial Clock and Data Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. See Figure 11. Serial Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. Serial Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the device into the Standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus. Serial Acknowledge Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. See Figure 12. The device will respond with an acknowledge after recognition of a start condition and if the correct Device Identifier and Select bits are contained in the Slave Address Byte. If a write operation is selected, the device will respond with an acknowledge after the receipt of each subsequent eight bit word. The device will acknowledge all incoming data and address bytes, except for the Slave Address Byte when the Device Identifier and/or Select bits are incorrect.
SCL
SDA Start Stop
Figure 12.Acknowledge Response From Receiver
SCL from Master Data Output from Transmitter Data Output from Receiver Start Acknowledge
1
8
9
DEVICE ADDRESSING Addressing Protocol Overview Depending upon the operation to be performed on each of these individual parts, a 1, 2 or 3 Byte protocol is used. All operations however must begin with the Slave Address Byte being clocked into the SMBus port on the SCL and SDA pins. The Slave address selects the part of the device to be addressed, and specifies if a Read or Write operation is to be performed. Slave Address Byte Following a START condition, the master must output a Slave Address Byte. This byte consists of three parts: - The Device Type Identifier which consists of the most significant four bits of the Slave Address (SA7 - SA4). The Device Type Identifier MUST be set to 1010 in order to select the device. - The next two bits (SA3 - SA2) are slave address bits. The bits received via the SMBus are compared to A0 and A1 pins and must match or the communication is aborted.
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X80140/41/42/43/44 - Preliminary Information
- The next bit, SA1, selects the device memory sector. There are two addressable sectors: the memory array and the control, fault detection and remote shutdown registers. - The Least Significant Bit of the Slave Address (SA0) Byte is the R/W bit. This bit defines the operation to be performed. When the R/W bit is "1", then a READ operation is selected. A "0" selects a WRITE operation (Refer toFigure 13). Figure 13.Slave Address Format
DEVICE TYPE IDENTIFIER SA7 SA6 SA5 EXTERNAL Memory READ / DEVICE ADDRESS Select WRITE SA4 SA3 SA2 SA1 SA0
Data Byte, the device again responds with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the device begins the internal write cycle to the nonvolatile memory. During this internal write cycle, the device inputs are disabled, so the device will not respond to any requests from the master. The SDA output is at high impedance. A write to a protected block of memory will suppress the acknowledge bit. PAGE WRITE The device is capable of a page write operation. See Figure 14. It is initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the first data byte is transferred, the master can transmit an unlimited number of 8-bit bytes. After the receipt of each byte, the device will respond with an acknowledge, and the address is internally incremented by one. The page address remains constant. When the counter reaches the end of the page, it "rolls over" and goes back to `0' on the same page. See Figure 15. This means that the master can write 16 bytes to the page starting at any location on that page. If the master begins writing at location 10, and loads 12 bytes, then the first 6 bytes are written to locations 10 through 15, and the last 6 bytes are written to locations 0 through 5. Afterwards, the address counter would point to location 6 of the page that was just written. If the master supplies more than 16 bytes of data, then new data overwrites the previous data, one byte at a time. The master terminates the Data Byte loading by issuing a stop condition, which causes the device to begin the nonvolatile write cycle. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. STOPS AND WRITE MODES Stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte plus the subsequent ACK signal. If a stop is issued in the middle of a data byte, or before 1 full data byte plus its associated ACK is sent, then the device will reset itself without performing the write. The contents of the array will not be effected. ACKNOWLEDGE POLLING The disabling of the inputs during high voltage cycles can be used to take advantage of the typical 5ms write cycle time. Once the stop condition is issued to indicate the end of the master's byte load operation, the device initiates the internal high voltage cycle. Acknowledge polling can be initiated immediately. To do this, the master issues a start condition followed by the Slave Address Byte for a write or read operation. If the device is still busy with the high voltage cycle then no ACK will be returned. If the device has completed the write operation, an ACK will be returned and the host can then proceed with the read or write operation. See Figure 18.
1
0
1
0
A1
A0
MS R/W
Internal Address (SA1) 0 1
Internally Addressed Device EEPROM Array Control Register, Fault Detection Register
Bit SA0 0 1
Operation WRITE READ
Serial Write Operations Before any write operations can be performed, a programming supply voltage (VP) must be supplied. This voltage is only needed for programming, but the nonvolatile registers and EEPROM locations cannot be programmed without it. In order to successfully complete a write operation to either a Control Register or the EEPROM array, the Write Enable Latch (WEL) bit must first be set and either the WP pin or the WPEN bit must be LOW. Writes to the WEL bit do not cause a high voltage write cycle, so the device is ready for the next operation immediately after the stop condition. BYTE WRITE For a write operation, the device requires the Slave Address Byte and a Word Address Byte. This gives the master access to any one of the words in the array. After receipt of the Word Address Byte, the device responds with an acknowledge, and awaits the next eight bits of data. After receiving the 8 bits of the
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X80140/41/42/43/44 - Preliminary Information
Figure 14.Page Write Operation
S t a r t (1 to n to 16) Slave Address Byte Address Data (1) Data (n) S t o p
Signals from the Master SDA Bus
1010 Signals from the Slave
0 A C K A C K A C K A C K
Figure 15.Writing 12 bytes to a 16-byte page starting at location 10.
7 Bytes
address pointer ends here Addr = 7 address 10
5 Bytes
address =6
address n-1
Figure 16.Random Address Read Sequence
Signals from the Master S t a r t Slave Address Byte Address S t a r t Slave Address S t o p 1 A C K
SDA Bus Signals from the Slave
1010
0 A C K A C K
1010
Data
Figure 17.Current Address Read Sequence.
S t a r t Slave Address S t o p
Signals from the Master
SDA Bus Signals from the Slave
1010
1 A C K
Data
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X80140/41/42/43/44 - Preliminary Information
Figure 18.Acknowledge Polling Sequence
Byte Load Completed by Issuing STOP. Enter ACK Polling
CURRENT ADDRESS READ Internally the device contains an address counter that maintains the address of the last word read incremented by one. Therefore, if the last read was to address n, the next read operation would access data from address n+1. On power up, the address of the address counter is undefined, requiring a read or write operation for initialization. Upon receipt of the Slave Address Byte with the R/W bit set to one, the device issues an acknowledge and then transmits the eight bits of the Data Byte. The master terminates the read operation when it does not respond with an acknowledge during the ninth clock and then issues a stop condition. See Figure 17 or the address, acknowledge, and data transfer sequence. Operational Notes The device powers-up in the following state:
Issue START
Issue Slave Address Byte (Read or Write)
Issue STOP
ACK Returned? YES High Voltage Cycle Complete. Continue Command Sequence?
NO
- The device is in the low power standby state. - The WEL bit is set to `0'. In this state it is not possible to write to the device.
Issue STOP NO
- SDA pin is the input mode. Data Protection
YES Continue Normal Read or Write Command Sequence
The following circuitry has been included to prevent inadvertent writes: - The WEL bit must be set to allow write operations. - The proper clock count and bit sequence is required prior to the stop bit in order to start a nonvolatile write cycle.
PROCEED
- The WP pin, when held HIGH, prevents all writes to the array and all the Register. - A programming voltage must be applied to the VP pin prior to any programming sequence.
Serial Read Operations Read operations are initiated in the same manner as write operations with the exception that the R/W bit of the Slave Address Byte is set to one. There are three basic read operations: Current Address Reads, Random Reads, and Sequential Reads. RANDOM READ Random read operation allows the master to access any memory location in the array. Prior to issuing the Slave Address Byte with the R/W bit set to one, the master must first perform a "dummy" write operation. The master issues the start condition and the Slave Address Byte, receives an acknowledge, then issues the Word Address Bytes. After acknowledging receipts of the Word Address Bytes, the master immediately issues another start condition and the Slave Address Byte with the R/W bit set to one. This is followed by an acknowledge from the device and then by the eight bit word. The master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. See Figure 16 for the address, acknowledge, and data transfer sequence.
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X80140/41/42/43/44 - Preliminary Information
PACKAGING INFORMATION
20-Lead Quad Flat No Lead Package (Package Code: Q) 5mm x 5mm Body with 0.65mm Lead Pitch
Pin 1 Indent A1
b
E
E2
e
y
D2
D
A
Dimensions in Millimeters Symbols A A1 b C D D2 E E2 e L y Min 0.70 0.00 0.23 0.19 4.90 -- 4.90 -- -- 0.35 0.00 Nom 0.75 0.02 0.30 0.20 5.00 3.10 5.00 3.10 0.65 0.55 -- Max 0.80 0.05 0.38 0.25 5.10 -- 5.10 -- -- 0.75 0.076
Note: 1. The package outline drawing is compatilbe
with JEDEC MO-220; variations: WHHC. 2. The terminal #1 identifier is a laser marked feature
LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. COPYRIGHTS AND TRADEMARKS Xicor, Inc., the Xicor logo, E2POT, XDCP, XBGA, AUTOSTORE, Direct Write cell, Concurrent Read-Write, PASS, MPS, PushPOT, Block Lock, IdentiPROM, E2KEY, X24C16, SecureFlash, and SerialFlash are all trademarks or registered trademarks of Xicor, Inc. All other brand and product names mentioned herein are used for identification purposes only, and are trademarks or registered trademarks of their respective holders. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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